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Hardware Architecture

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Total of 32 entries
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Fri, 22 Nov 2024 (showing 7 of 7 entries )

[1] arXiv:2411.14299 [pdf, html, other]
Title: Auto-SPICE: Leveraging LLMs for Dataset Creation via Automated SPICE Netlist Extraction from Analog Circuit Diagrams
Jitendra Bhandari, Vineet Bhat, Yuheng He, Siddharth Garg, Hamed Rahmani, Ramesh Karri
Subjects: Hardware Architecture (cs.AR)
[2] arXiv:2411.14082 [pdf, html, other]
Title: CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations
Xiaoming Chen
Subjects: Hardware Architecture (cs.AR)
[3] arXiv:2411.13900 [pdf, html, other]
Title: Dissecting Conditional Branch Predictors of Apple Firestorm and Qualcomm Oryon for Software Optimization and Architectural Analysis
Jiajie Chen, Peng Qu, Youhui Zhang
Subjects: Hardware Architecture (cs.AR)
[4] arXiv:2411.13717 [pdf, other]
Title: Hardware Accelerators for Artificial Intelligence
S M Mojahidul Ahsan, Anurag Dhungel, Mrittika Chowdhury, Md Sakib Hasan, Tamzidul Hoque
Comments: The book chapter is a part of the Book, "AI-Enabled Electronic Circuit and System Design" with ISBN 978-3-031-71435-1
Subjects: Hardware Architecture (cs.AR); Emerging Technologies (cs.ET)
[5] arXiv:2411.14006 (cross-list from cs.DS) [pdf, html, other]
Title: Experimental comparison of graph-based approximate nearest neighbor search algorithms on edge devices
Ali Ganbarov, Jicheng Yuan, Anh Le-Tuan, Manfred Hauswirth, Danh Le-Phuoc
Subjects: Data Structures and Algorithms (cs.DS); Hardware Architecture (cs.AR); Computer Vision and Pattern Recognition (cs.CV); Distributed, Parallel, and Cluster Computing (cs.DC); Performance (cs.PF)
[6] arXiv:2411.13715 (cross-list from physics.optics) [pdf, html, other]
Title: SimPhony: A Device-Circuit-Architecture Cross-Layer Modeling and Simulation Framework for Heterogeneous Electronic-Photonic AI System
Ziang Yin, Meng Zhang, Amir Begovic, Rena Huang, Jeff Zhang, Jiaqi Gu
Comments: 7-page
Subjects: Optics (physics.optics); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Emerging Technologies (cs.ET); Machine Learning (cs.LG)
[7] arXiv:2411.13571 (cross-list from math.NA) [pdf, html, other]
Title: A low-rank balanced truncation approach for large-scale RLCk model order reduction based on extended Krylov subspace and a frequency-aware convergence criterion
Christos Giamouzis, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis
Comments: arXiv admin note: substantial text overlap with arXiv:2311.08478
Subjects: Numerical Analysis (math.NA); Hardware Architecture (cs.AR); Computational Engineering, Finance, and Science (cs.CE)

Thu, 21 Nov 2024 (showing 5 of 5 entries )

[8] arXiv:2411.13054 [pdf, html, other]
Title: Generalized Ping-Pong: Off-Chip Memory Bandwidth Centric Pipelining Strategy for Processing-In-Memory Accelerators
Ruibao Wang, Bonan Yan
Subjects: Hardware Architecture (cs.AR)
[9] arXiv:2411.13050 [pdf, html, other]
Title: Topkima-Former: Low-energy, Low-Latency Inference for Transformers using top-k In-memory ADC
Shuai Dong, Junyi Yang, Xiaoqi Peng, Hongyang Shang, Ye Ke, Xiaofeng Yang, Hongjie Liu, Arindam Basu
Comments: 7 pages
Subjects: Hardware Architecture (cs.AR)
[10] arXiv:2411.12983 [pdf, other]
Title: Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog
Naoya Hatta, Taichi Ishitani, Ryota Shioya
Comments: 6 pages, 6 figures, Published in DVCon Japan 2024
Subjects: Hardware Architecture (cs.AR)
[11] arXiv:2411.13239 (cross-list from cs.DC) [pdf, other]
Title: Transforming the Hybrid Cloud for Emerging AI Workloads
Deming Chen, Alaa Youssef, Ruchi Pendse, André Schleife, Bryan K. Clark, Hendrik Hamann, Jingrui He, Teodoro Laino, Lav Varshney, Yuxiong Wang, Avirup Sil, Reyhaneh Jabbarvand, Tianyin Xu, Volodymyr Kindratenko, Carlos Costa, Sarita Adve, Charith Mendis, Minjia Zhang, Santiago Núñez-Corrales, Raghu Ganti, Mudhakar Srivatsa, Nam Sung Kim, Josep Torrellas, Jian Huang, Seetharami Seelam, Klara Nahrstedt, Tarek Abdelzaher, Tamar Eilam, Huimin Zhao, Matteo Manica, Ravishankar Iyer, Martin Hirzel, Vikram Adve, Darko Marinov, Hubertus Franke, Hanghang Tong, Elizabeth Ainsworth, Han Zhao, Deepak Vasisht, Minh Do, Fabio Oliveira, Giovanni Pacifici, Ruchir Puri, Priya Nagpurkar
Comments: 70 pages, 27 figures
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Emerging Technologies (cs.ET); Multiagent Systems (cs.MA)
[12] arXiv:2411.12923 (cross-list from cs.LO) [pdf, html, other]
Title: Towards Automated Verification of Logarithmic Arithmetic
Mark G. Arnold, Thomas A. Bailey, John R. Cowles
Comments: 21 pages, Originally a 1994 technical report from University of Wyoming and Computational Logic, Inc
Subjects: Logic in Computer Science (cs.LO); Hardware Architecture (cs.AR)

Wed, 20 Nov 2024 (showing 7 of 7 entries )

[13] arXiv:2411.12710 [pdf, html, other]
Title: Travel Time Based Task Mapping for NoC-Based DNN Accelerator
Yizhi Chen, Wenyao Zhu, Zhonghai Lu
Comments: Accepted to SAMOS 2024 (SAMOS XXIV International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation June 29 - July 4, 2024)
Subjects: Hardware Architecture (cs.AR)
[14] arXiv:2411.12444 [pdf, other]
Title: Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
George-Marios Fragkoulis, Nikos Karystinos, George Papadimitriou, Dimitris Gizopoulos
Comments: 8 pages, 6 figures, CARRV '24, November 3rd, 2024, Co-located with IEEE/ACM MICRO 2024
Subjects: Hardware Architecture (cs.AR)
[15] arXiv:2411.12213 [pdf, html, other]
Title: Forward and Reverse Converters for the Moduli-Set $\{2^{2q+1},2^q+2^{q-1}\pm1\}$
Ghassem Jaberipur, Bardia Nadimi, R. Kazemi, Jeong-A Lee
Subjects: Hardware Architecture (cs.AR); Signal Processing (eess.SP)
[16] arXiv:2411.11856 [pdf, html, other]
Title: Can EDA Tool Feedback Improve Verilog Generation by LLMs?
Jason Blocklove, Shailja Thakur, Benjamin Tan, Hammond Pearce, Siddharth Garg, Ramesh Karri
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Programming Languages (cs.PL)
[17] arXiv:2411.11852 [pdf, html, other]
Title: LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference
Yanyue Xie, Zhengang Li, Dana Diaconu, Suranga Handagala, Miriam Leeser, Xue Lin
Comments: Accepted by ASPDAC 2025
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)
[18] arXiv:2411.12583 (cross-list from cs.PF) [pdf, html, other]
Title: Examem: Low-Overhead Memory Instrumentation for Intelligent Memory Systems
Ashwin Poduval, Hayden Coffey, Michael Swift
Comments: 11 pages + references, 13 figures
Subjects: Performance (cs.PF); Hardware Architecture (cs.AR)
[19] arXiv:2411.12401 (cross-list from quant-ph) [pdf, html, other]
Title: Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing
Xiaorang Guo, Jonas Winklmann, Dirk Stober, Amr Elsharkawy, Martin Schulz
Comments: The paper is accepted by Design, Automation and Test in Europe Conference (DATE), 2025
Subjects: Quantum Physics (quant-ph); Hardware Architecture (cs.AR); Emerging Technologies (cs.ET)

Tue, 19 Nov 2024 (showing 10 of 10 entries )

[20] arXiv:2411.11545 [pdf, html, other]
Title: An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors
Zhe Su, Aron Bencsik, Giacomo Indiveri, Davide Bertozzi
Subjects: Hardware Architecture (cs.AR); Neural and Evolutionary Computing (cs.NE)
[21] arXiv:2411.11384 [pdf, html, other]
Title: SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
Giovanni Brignone, Roberto Bosio, Fabrizio Ottati, Claudio Sansoè, Luciano Lavagno
Subjects: Hardware Architecture (cs.AR)
[22] arXiv:2411.11022 [pdf, html, other]
Title: ASiM: Improving Transparency of SRAM-based Analog Compute-in-Memory Research with an Open-Source Simulation Framework
Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Kentaro Yoshioka
Comments: 12 pages, 13 figures
Subjects: Hardware Architecture (cs.AR)
[23] arXiv:2411.10990 [pdf, html, other]
Title: Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer
Xiangfei Hu, Yuyang Ye, Tinghuan Chen, Hao Yan, Bei Yu
Subjects: Hardware Architecture (cs.AR)
[24] arXiv:2411.10988 [pdf, html, other]
Title: AppSign: Multi-level Approximate Computing for Real-Time Traffic Sign Recognition in Autonomous Vehicles
Fatemeh Omidian, Athena Abdi
Subjects: Hardware Architecture (cs.AR); Computer Vision and Pattern Recognition (cs.CV)
[25] arXiv:2411.11745 (cross-list from cs.LG) [pdf, html, other]
Title: BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration
Yuzong Chen, Ahmed F. AbouElhamayed, Xilai Dai, Yang Wang, Marta Andronic, George A. Constantinides, Mohamed S. Abdelfattah
Comments: HPCA 2025
Subjects: Machine Learning (cs.LG); Hardware Architecture (cs.AR)
[26] arXiv:2411.11678 (cross-list from physics.ins-det) [pdf, html, other]
Title: Analysis of Hardware Synthesis Strategies for Machine Learning in Collider Trigger and Data Acquisition
Haoyi Jia, Abhilasha Dave, Julia Gonski, Ryan Herbst
Comments: 12 pages, 5 figures
Subjects: Instrumentation and Detectors (physics.ins-det); Hardware Architecture (cs.AR); Machine Learning (cs.LG); High Energy Physics - Experiment (hep-ex)
[27] arXiv:2411.11624 (cross-list from cs.CR) [pdf, other]
Title: Teapot: Efficiently Uncovering Spectre Gadgets in COTS Binaries
Fangzheng Lin, Zhongfa Wang, Hiroshi Sasaki
Comments: To appear in ACM/IEEE International Symposium on Code Generation and Optimization (CGO) 2025
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
[28] arXiv:2411.11036 (cross-list from cs.PL) [pdf, html, other]
Title: Scaling Program Synthesis Based Technology Mapping with Equality Saturation
Gus Henry Smith, Colin Knizek, Daniel Petrisko, Zachary Tatlock, Jonathan Balkind, Gilbert Louis Bernstein, Haobin Ni, Chandrakana Nandi
Comments: Workshop on Open-Source EDA Technology (WOSET) 2024
Subjects: Programming Languages (cs.PL); Hardware Architecture (cs.AR)
[29] arXiv:2411.10481 (cross-list from cs.LG) [pdf, other]
Title: Boolean-aware Boolean Circuit Classification: A Comprehensive Study on Graph Neural Network
Liwei Ni, Xinquan Li, Biwei Xie, Huawei Li
Subjects: Machine Learning (cs.LG); Hardware Architecture (cs.AR)

Mon, 18 Nov 2024 (showing 3 of 3 entries )

[30] arXiv:2411.10285 [pdf, html, other]
Title: Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
Pedro Palacios, Rafael Medina, Jean-Luc Rouas, Giovanni Ansaloni, David Atienza
Comments: 7 pages, 10 figures
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
[31] arXiv:2411.09760 [pdf, html, other]
Title: SpecPCM: A Low-power PCM-based In-Memory Computing Accelerator for Full-stack Mass Spectrometry Analysis
Keming Fan, Ashkan Moradifirouzabadi, Xiangjin Wu, Zheyu Li, Flavio Ponzina, Anton Persson, Eric Pop, Tajana Rosing, Mingu Kang
Subjects: Hardware Architecture (cs.AR); Emerging Technologies (cs.ET); Signal Processing (eess.SP)
[32] arXiv:2411.10005 (cross-list from cs.DB) [pdf, html, other]
Title: Analyzing Performance Characteristics of PostgreSQL and MariaDB on NVMeVirt
Juhee Han, Yoojin Choi
Subjects: Databases (cs.DB); Hardware Architecture (cs.AR)
Total of 32 entries
Showing up to 50 entries per page: fewer | more | all